-
[ Pobierz całość w formacie PDF ]
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device s electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.
23
MBM29F800TA-55/-70/-90/MBM29F800BA-55/-70/-90
MAXIMUM OVERSHOOT
20 ns 20 ns
+0.8 V
0.5 V
2.0 V
20 ns
Figure 1 Maximum Negative Overshoot Waveform
20 ns
VCC+2.0 V
VCC+0.5 V
+2.0 V
20 ns 20 ns
Figure 2 Maximum Positive Overshoot Waveform 1
20 ns
+14.0 V
+13.0 V
VCC+0.5 V
20 ns 20 ns
Note: This waveform is applied for A9, OE, and RESET.
Figure 3 Maximum Positive Overshoot Waveform 2
24
MBM29F800TA-55/-70/-90/MBM29F800BA-55/-70/-90
DC CHARACTERISTICS
Parameter
Parameter Description Test Conditions Min. Max. Unit
Symbol
ILI Input Leakage Current VIN = VSS to VCC, VCC = VCC Max. 1.0 +1.0 A
ILO Output Leakage Current VOUT = VSS to VCC, VCC = VCC Max. 1.0 +1.0 A
A9, OE, RESET Inputs Leakage VCC = VCC Max.
ILIT 50 A
Current A9, OE, RESET = 12.5 V
Byte 38
ICC1 VCC Active Current (Note 1) CE = VIL, OE = VIH mA
Word 45
ICC2 VCC Active Current (Note 2) CE = VIL, OE = VIH 50 mA
VCC = VCC Max., CE = VIH,
1 mA
RESET = VIH
ICC3 VCC Current (Standby)
VCC = VCC Max., CE = VCC 0.3 V,
5 A
RESET = VCC 0.3 V
VCC = VCC Max.,
1 mA
RESET = VIL
ICC4 VCC Current (Standby, Reset)
VCC = VCC Max.,
5 A
RESET = VSS 0.3 V
VIL Input Low Level 0.5 0.8 V
VIH Input High Level 2.0 VCC + 0.5 V
Voltage for Autoselect and
VID Sector Protection 11.5 12.5 V
(A9, OE, RESET) (Note 3, 4)
VOL Output Low Voltage Level IOL = 5.8mA, VCC = VCC Min. 0.45 V
VOH1 IOH = 2.5 mA, VCC = VCC Min. 2.4 V
Output High Voltage Level
VOH2 IOH = 100 A VCC 0.4 V
VLKO Low VCC Lock-Out Voltage 3.2 4.2 V
Notes: 1. The ICC current listed includes both the DC operating current and the frequency dependent component
(at 6 MHz). The frequency component typically is 2 mA/MHz, with OE at VIH.
2. ICC active while Embedded Algorithm (program or erase) is in progress.
3. Applicable to sector protection function.
4. (VID VCC) do not exceed 9 V.
25
MBM29F800TA-55/-70/-90/MBM29F800BA-55/-70/-90
AC CHARACTERISTICS
" Read Only Operations Characteristics
Parameter
MBM29F800TA/BA
Symbols
Description Test Setup Unit
-55 -70 -90
JEDEC Standard
(Note1) (Note2) (Note2)
tAVAV tRC Read Cycle Time Min. 55 70 90 ns
CE = VIL
tAVQV tACC Address to Output Delay Max. 55 70 90 ns
OE = VIL
tELQV tCE Chip Enable to Output Delay OE = VIL Max. 55 70 90 ns
tGLQV tOE Output Enable to Output Delay Max. 30 30 40 ns
tEHQZ tDF Chip Enable to Output High-Z Max. 15 20 20 ns
tGHQZ tDF Output Enable to Output High-Z Max. 15 20 20 ns
Output Hold Time From
tAXQX tOH Min. 0 0 0 ns
Addresses, CE or OE, Whichever
Occurs First
tREADY RESET Pin Low to Read Mode Max. 20 20 20 s
tELFL CE or BYTE Switching Low or
Max. 5 5 5 ns
tELFH High
Note: 2. Test Conditions:
Note: 1. Test Conditions:
Output Load: 1 TTL gate and 100 pF
Output Load: 1 TTL gate and 30 pF
Input rise and fall times: 5 ns
Input rise and fall times: 5 ns
Input pulse levels: 0.45 V to 2.4 V
Input pulse levels: 0.0 V to 3.0 V
Timing measurement reference level
Timing measurement reference level
Input: 0.8 V and 2.0 V
Input: 1.5 V
Output: 0.8 V and 2.0 V
Output: 1.5 V
5.0 V
IN3064
2.7 k&!
or Equivalent
Device
Under
Test
6.2 k&!
CL
Diodes = IN3064
or Equivalent
Notes: 1. CL = 30 pF including jig capacitance (MBM29F800TA/BA-55)
2. CL = 100 pF including jig capacitance (MBM29F800TA/BA-70/-90)
Figure 4 Test Conditions
26
MBM29F800TA-55/-70/-90/MBM29F800BA-55/-70/-90
" Write/Erase/Program Operations
Parameter Symbols MBM28F800TA/BA
Description Unit
JEDEC Standard -55 -70 -90
tAVAV tWC Write Cycle Time Min. 55 70 90 ns
tAVWL tAS Address Setup Time Min. 0 0 0 ns
tWLAX tAH Address Hold Time Min. 40 45 45 ns
tDVWH tDS Data Setup Time Min. 25 30 45 ns
tWHDX tDH Data Hold Time Min. 0 0 0 ns [ Pobierz całość w formacie PDF ] - zanotowane.pl
- doc.pisz.pl
- pdf.pisz.pl
- zambezia2013.opx.pl